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This site contains information on my Master's Thesis Measurement Board design.
Measurement Board Control FPGA Information:
- Control FPGA ERS
Information on Peripheral devices, etc... - Measurement Board Custom EDK Peripherals located at /tmp2/jwwebb/measbd/sw/ on pepper.ece.ucdavis.edu
To download code use: rsync -avz pepper.ece.ucdavis.edu:/tmp2/jwwebb/measbd/sw/ sw/To upload code use: rsync -avz sw/ pepper.ece.ucdavis.edu:/tmp2/jwwebb/measbd/sw/ - AsAP SPI Engine EDK Peripheral Notes
Register Descriptions, and SPIE instantiation.asap_config_v1_00_a EDK Peripheral Register Map Address Name R/W Default Value Description 0 config_data[31:0] R/W 0x00000000 Lower 32-bits of Configuration Data. 1 {24'b0,config_data[39:32]} R/W 0x00000000 Upper 8-bits of Configuration Data. 2 config_addr[31:0] R/W 0x00000000 Lower 32-bits of Configuration Address. 3 {24'b0,config_addr[39:32]} R/W 0x00000000 Upper 8-bits of Configuration Address. 4 {29'b0,spie_cfg[2:0]} R/W 0x00000006 SPIE Configuration Register:
0: start_spi; start SPIE transaction by toggling l-h-l. (Active High)
1: reset_cold; perform cold reset on AsAP by toggling h-l-h. (Active Low)
2: reset_sel;0 -> 20ns wide retimed pulse.
1 -> uBlaze pulse h-l-h.5 slv_reg5[31:0] R/W 0x00000000 Reserved Register. 6 {29'b0,spie_stat[2:0]} R 0x00000000 SPIE Status Register:
0: miso_rdy; MISO data is ready to be read from SPIE. (Active High)
1: send; SPIE ready to start a new transaction. (Active High)
2: hold;0 -> receiving data/addr.
1 -> transaction in process.7 {12'b0,miso_read[19:0]} R 0x00000000 SPIE MISO Read Data.
- Software Development Documentation
C code function Descriptions, and code blocks. - Software Development MicroSD Driver Documentation
C code function Descriptions, and code blocks. - Software Development AsAP Configuration Driver Documentation
C code function Descriptions, and code blocks. - AsAP SPI Engine EDK Peripheral
Download and unzip in C:\edk_user_repository\MyProcessorIPLib\ directory. - Sample EDK Project using the AsAP SPI Engine EDK Peripheral Notes
Instantiates 2 asap_config_v1_00_a EDK Peripherals and connects SPI signals to FPGA Pins. - Xilinx Spartan-3E XC3S1600E Eval Board Information - datasheets, user guides, ...
- Xilinx Spartan-3 XC3S1500 Eval Board Information - datasheets, user guides, ...
- Avnet Virtex-5 LX50 Eval Board Information - datasheets, user guides, ...
Jeremy W. Webb Graduate Student Electrical and Computer Engineering Department One Shields Avenue Davis, CA 95616
Last Modified: Monday, March 27, 2017 10:20:49 PM
