#******************************************************************
#
# spie_mb_notes.txt module
#
#******************************************************************
#
# VLSI Computation Lab Confidential Copyright © 2008 UC Davis 
#
#******************************************************************
#
# created on:	07/17/2008 
# created by:	jwwebb
# last edit on:	$DateTime: $ 
# last edit by:	$Author: $
# revision:	$Revision: $
# comments:	Generated.
#
# board name:		MSEE Multipurpose Measurement Board
# board number:		p342
# board revision:	001
# device mpn:		XC3S1400A-4FGG484C
# 
#******************************************************************

#---------------------------------------------------------
# S O F T W A R E  U S E R  L O G I C  R E G I S T E R S
#---------------------------------------------------------
Software Registers (32-bits by default):

----------------------------------------------------------------------------------
Address         Name                    Description
----------------------------------------------------------------------------------
   0       config_data[31:0]            Lower 32-bits of Configuration Data.
   1       {24'b0,config_data[39:32]}   Upper 8-bits of Configuration Data.
   2       config_addr[31:0]            Lower 32-bits of Configuration Address.
   3       {24'b0,config_addr[39:32]}   Upper 8-bits of Configuration Address.
   4       {29'b0,spie_cfg[2:0]}        SPIE Configuration Register:
                                        0: start_spi; start SPIE transaction by toggling l-h-l. (Active High)
                                        1: reset_cold; perform cold reset on AsAP by toggling h-l-h. (Active Low)
                                        2: reset_sel;   0 -> 20ns wide retimed pulse, 
                                                        1 -> uBlaze pulse h-l-h
   5       slv_reg5[31:0]               Reserved Register
   6       {29'b0,spie_stat[2:0]}       SPIE Status Register:
                                        0: miso_rdy; miso data is ready to be read.(Active High)
                                        1: send; SPIE ready to start a new transaction. (Active High)
                                        2: hold; SPIE in process of current transaction. (Active High)
                                                        0 -> receiving data/addr.
                                                        1 -> transaction in process.
   7       {12'b0,miso_read[19:0]}      SPIE MISO Read Data.
----------------------------------------------------------------------------------

#--------------------------------------
# S P I E  I N S T A N T I A T I O N
#--------------------------------------

The spie controller will be instantiated into the 
file "user_logic.v". The signals that need to 
connect to the FPGA inputs and outputs will need 
to be added as ports in user_logic.v.  These new
ports will then need to be added to the VHDL file
"asap_config.vhd". In addition, the signals that 
need to connect to the FPGA inputs and outputs 
will need to be added as ports in "asap_config.vhd".
This will make the AsAP SPI and Config signals 
accessible to the EDK/XPS GUI; the PORTS tab.

# *** Instantiate the SPI Master Engine ***
spie   _spie   (.clk_50 (clk_50),
	        .rst_n (rst_n),
          	.MISO (MISO),
	        .config_data (config_data),
                .config_addr (config_addr),
                .start_spi (start_spi),
                .stop_spi (stop_spi),
                .hold (hold),
                .send (send),
                .miso_rdy (miso_rdy),
                .config_clk (config_clk),
                .config_valid (config_valid),
                .SCK (SCK),
                .CSn (CSn),
                .MOSI (MOSI),
                .LOAD_EN (LOAD_EN),
                .miso_read (miso_read));

#--------------------------------------
# ASAP_CONFIG_V1_00_A EDK Peripheral
#--------------------------------------

Now that the asap_config_v1_00_a EDK peripheral 
has been created, it needs to be imported into 
EDK/XPS. The peripheral will be connected to the 
PLB bus, and is a Mixed HDL design. Use the 
asap_config_v1_00_a.mpd and asap_config_v1_00_a.prj
files to point to the necessary HDL design files.
This peripheral does not use interrupts. Descriptions
can be added to each signal in the peripheral import 
wizard. Now the asap_config peripheral will be available
in the IP Catalog in the EDK/XPS GUI.