Today is: Tuesday April 23, 2024
Welcome to the MSEE Thesis Board QDR-II SRAM Delay web page. This page
contains information on the approximate IODELAY taps required on the
QDR-II SRAM Read and Write signals. The Perl code for used to implement
the table below is provided in a gzip'd tar-ball: qdrii_sram_iodelay.tgz.
QDR-II SRAM Signal IODELAY Taps:
- Matched Length Group #1: SIG_DML1_CON, Reference Signal: FPGA_SRAM_K_CLK_P
- Matched Length Group #2: SIG_DML2_CON, Reference Signal: FPGA_SRAM_CQ_CLK_P
- Matched Length Group #3: SIG_DML3_CON, Reference Signal: FPGA_SRAM_CQ_CLK_N
| Signal Name | Length (Mils) | ML Group | Is Reference | Average Length (Mils) | Length (ps) | Added Delay (ps) | Number of Taps Needed | Number of Taps Needed (Normalized) |
|---|---|---|---|---|---|---|---|---|
| Matched Length Group #1 | ||||||||
| FPGA_SRAM_ADDR17 | 4604.33 | SIG_DML1_CON | 0 | 2861.18174603175 | 768.92311 | -329.96361 | -4 | 0 |
| FPGA_SRAM_ADDR16 | 3819.12 | SIG_DML1_CON | 0 | 2861.18174603175 | 637.79304 | -198.83354 | -2 | 2 |
| FPGA_SRAM_ADDR15 | 3373.71 | SIG_DML1_CON | 0 | 2861.18174603175 | 563.40957 | -124.45007 | -1 | 3 |
| FPGA_SRAM_ADDR14 | 2694.44 | SIG_DML1_CON | 0 | 2861.18174603175 | 449.97148 | -11.01198 | 0 | 4 |
| FPGA_SRAM_ADDR13 | 2530.12 | SIG_DML1_CON | 0 | 2861.18174603175 | 422.53004 | 16.4294600000001 | 0 | 4 |
| FPGA_SRAM_ADDR12 | 2476.1 | SIG_DML1_CON | 0 | 2861.18174603175 | 413.5087 | 25.4508 | 0 | 4 |
| FPGA_SRAM_ADDR11 | 3864.65 | SIG_DML1_CON | 0 | 2861.18174603175 | 645.39655 | -206.43705 | -2 | 2 |
| FPGA_SRAM_ADDR10 | 3629.69 | SIG_DML1_CON | 0 | 2861.18174603175 | 606.15823 | -167.19873 | -2 | 2 |
| FPGA_SRAM_ADDR9 | 3037.2 | SIG_DML1_CON | 0 | 2861.18174603175 | 507.2124 | -68.2529 | 0 | 4 |
| FPGA_SRAM_ADDR8 | 2574.04 | SIG_DML1_CON | 0 | 2861.18174603175 | 429.86468 | 9.09482000000003 | 0 | 4 |
| FPGA_SRAM_ADDR7 | 3324.62 | SIG_DML1_CON | 0 | 2861.18174603175 | 555.21154 | -116.25204 | -1 | 3 |
| FPGA_SRAM_ADDR6 | 3145.99 | SIG_DML1_CON | 0 | 2861.18174603175 | 525.38033 | -86.4208299999999 | -1 | 3 |
| FPGA_SRAM_ADDR5 | 2671.76 | SIG_DML1_CON | 0 | 2861.18174603175 | 446.18392 | -7.22442000000001 | 0 | 4 |
| FPGA_SRAM_ADDR4 | 3057.69 | SIG_DML1_CON | 0 | 2861.18174603175 | 510.63423 | -71.67473 | 0 | 4 |
| FPGA_SRAM_ADDR3 | 3591.46 | SIG_DML1_CON | 0 | 2861.18174603175 | 599.77382 | -160.81432 | -2 | 2 |
| FPGA_SRAM_ADDR2 | 2905.65 | SIG_DML1_CON | 0 | 2861.18174603175 | 485.24355 | -46.28405 | 0 | 4 |
| FPGA_SRAM_ADDR1 | 2879.98 | SIG_DML1_CON | 0 | 2861.18174603175 | 480.95666 | -41.99716 | 0 | 4 |
| FPGA_SRAM_ADDR0 | 2616.2 | SIG_DML1_CON | 0 | 2861.18174603175 | 436.9054 | 2.05410000000006 | 0 | 4 |
| FPGA_SRAM_RDN | 2715 | SIG_DML1_CON | 0 | 2861.18174603175 | 453.405 | -14.4455 | 0 | 4 |
| FPGA_SRAM_BWN3 | 2604.82 | SIG_DML1_CON | 0 | 2861.18174603175 | 435.00494 | 3.95456000000001 | 0 | 4 |
| FPGA_SRAM_BWN2 | 2445.94 | SIG_DML1_CON | 0 | 2861.18174603175 | 408.47198 | 30.48752 | 0 | 4 |
| FPGA_SRAM_BWN1 | 2293.23 | SIG_DML1_CON | 0 | 2861.18174603175 | 382.96941 | 55.99009 | 0 | 4 |
| FPGA_SRAM_BWN0 | 3213.01 | SIG_DML1_CON | 0 | 2861.18174603175 | 536.57267 | -97.61317 | -1 | 3 |
| FPGA_SRAM_WRN | 2279.91 | SIG_DML1_CON | 0 | 2861.18174603175 | 380.74497 | 58.21453 | 0 | 4 |
| FPGA_SRAM_DLL_OFFN | 3008.41 | SIG_DML1_CON | 0 | 2861.18174603175 | 502.40447 | -63.44497 | 0 | 4 |
| FPGA_SRAM_K_CLK_P | 2628.5 | SIG_DML1_CON | 1 | 2861.18174603175 | 438.9595 | 0 | 0 | 4 |
| FPGA_SRAM_K_CLK_N | 2585.79 | SIG_DML1_CON | 0 | 2861.18174603175 | 431.82693 | 7.13257000000004 | 0 | 4 |
| FPGA_SRAM_WDATA35 | 3150.58 | SIG_DML1_CON | 0 | 2861.18174603175 | 526.14686 | -87.18736 | -1 | 3 |
| FPGA_SRAM_WDATA34 | 3050.75 | SIG_DML1_CON | 0 | 2861.18174603175 | 509.47525 | -70.51575 | 0 | 4 |
| FPGA_SRAM_WDATA33 | 2802.7 | SIG_DML1_CON | 0 | 2861.18174603175 | 468.0509 | -29.0914 | 0 | 4 |
| FPGA_SRAM_WDATA32 | 2562.85 | SIG_DML1_CON | 0 | 2861.18174603175 | 427.99595 | 10.9635500000001 | 0 | 4 |
| FPGA_SRAM_WDATA31 | 2276.92 | SIG_DML1_CON | 0 | 2861.18174603175 | 380.24564 | 58.71386 | 0 | 4 |
| FPGA_SRAM_WDATA30 | 2199.48 | SIG_DML1_CON | 0 | 2861.18174603175 | 367.31316 | 71.64634 | 0 | 4 |
| FPGA_SRAM_WDATA29 | 1792.9 | SIG_DML1_CON | 0 | 2861.18174603175 | 299.4143 | 139.5452 | 1 | 5 |
| FPGA_SRAM_WDATA28 | 1647.73 | SIG_DML1_CON | 0 | 2861.18174603175 | 275.17091 | 163.78859 | 2 | 6 |
| FPGA_SRAM_WDATA27 | 1730.36 | SIG_DML1_CON | 0 | 2861.18174603175 | 288.97012 | 149.98938 | 1 | 5 |
| FPGA_SRAM_WDATA26 | 3218.44 | SIG_DML1_CON | 0 | 2861.18174603175 | 537.47948 | -98.51998 | -1 | 3 |
| FPGA_SRAM_WDATA25 | 2953.25 | SIG_DML1_CON | 0 | 2861.18174603175 | 493.19275 | -54.23325 | 0 | 4 |
| FPGA_SRAM_WDATA24 | 2792.77 | SIG_DML1_CON | 0 | 2861.18174603175 | 466.39259 | -27.43309 | 0 | 4 |
| FPGA_SRAM_WDATA23 | 2563.12 | SIG_DML1_CON | 0 | 2861.18174603175 | 428.04104 | 10.91846 | 0 | 4 |
| FPGA_SRAM_WDATA22 | 1994.36 | SIG_DML1_CON | 0 | 2861.18174603175 | 333.05812 | 105.90138 | 1 | 5 |
| FPGA_SRAM_WDATA21 | 1963.23 | SIG_DML1_CON | 0 | 2861.18174603175 | 327.85941 | 111.10009 | 1 | 5 |
| FPGA_SRAM_WDATA20 | 1709.22 | SIG_DML1_CON | 0 | 2861.18174603175 | 285.43974 | 153.51976 | 1 | 5 |
| FPGA_SRAM_WDATA19 | 1825.79 | SIG_DML1_CON | 0 | 2861.18174603175 | 304.90693 | 134.05257 | 1 | 5 |
| FPGA_SRAM_WDATA18 | 2008.51 | SIG_DML1_CON | 0 | 2861.18174603175 | 335.42117 | 103.53833 | 1 | 5 |
| FPGA_SRAM_WDATA17 | 2557.84 | SIG_DML1_CON | 0 | 2861.18174603175 | 427.15928 | 11.80022 | 0 | 4 |
| FPGA_SRAM_WDATA16 | 2591.71 | SIG_DML1_CON | 0 | 2861.18174603175 | 432.81557 | 6.14393000000001 | 0 | 4 |
| FPGA_SRAM_WDATA15 | 2650.5 | SIG_DML1_CON | 0 | 2861.18174603175 | 442.6335 | -3.67399999999998 | 0 | 4 |
| FPGA_SRAM_WDATA14 | 2979.66 | SIG_DML1_CON | 0 | 2861.18174603175 | 497.60322 | -58.64372 | 0 | 4 |
| FPGA_SRAM_WDATA13 | 3128.26 | SIG_DML1_CON | 0 | 2861.18174603175 | 522.41942 | -83.45992 | -1 | 3 |
| FPGA_SRAM_WDATA12 | 3299.14 | SIG_DML1_CON | 0 | 2861.18174603175 | 550.95638 | -111.99688 | -1 | 3 |
| FPGA_SRAM_WDATA11 | 3631.04 | SIG_DML1_CON | 0 | 2861.18174603175 | 606.38368 | -167.42418 | -2 | 2 |
| FPGA_SRAM_WDATA10 | 3844.59 | SIG_DML1_CON | 0 | 2861.18174603175 | 642.04653 | -203.08703 | -2 | 2 |
| FPGA_SRAM_WDATA9 | 3883.33 | SIG_DML1_CON | 0 | 2861.18174603175 | 648.51611 | -209.55661 | -2 | 2 |
| FPGA_SRAM_WDATA8 | 2600.65 | SIG_DML1_CON | 0 | 2861.18174603175 | 434.30855 | 4.65095000000002 | 0 | 4 |
| FPGA_SRAM_WDATA7 | 2737.99 | SIG_DML1_CON | 0 | 2861.18174603175 | 457.24433 | -18.2848299999999 | 0 | 4 |
| FPGA_SRAM_WDATA6 | 2777.23 | SIG_DML1_CON | 0 | 2861.18174603175 | 463.79741 | -24.83791 | 0 | 4 |
| FPGA_SRAM_WDATA5 | 3063.23 | SIG_DML1_CON | 0 | 2861.18174603175 | 511.55941 | -72.59991 | 0 | 4 |
| FPGA_SRAM_WDATA4 | 3154.47 | SIG_DML1_CON | 0 | 2861.18174603175 | 526.79649 | -87.8369899999999 | -1 | 3 |
| FPGA_SRAM_WDATA3 | 3295.01 | SIG_DML1_CON | 0 | 2861.18174603175 | 550.26667 | -111.30717 | -1 | 3 |
| FPGA_SRAM_WDATA2 | 3659.74 | SIG_DML1_CON | 0 | 2861.18174603175 | 611.17658 | -172.21708 | -2 | 2 |
| FPGA_SRAM_WDATA1 | 3626.8 | SIG_DML1_CON | 0 | 2861.18174603175 | 605.6756 | -166.7161 | -2 | 2 |
| FPGA_SRAM_WDATA0 | 3958.94 | SIG_DML1_CON | 0 | 2861.18174603175 | 661.14298 | -222.18348 | -2 | 2 |
| Matched Length Group #2 | ||||||||
| FPGA_SRAM_CQ_CLK_P | 1976.35 | SIG_DML2_CON | 1 | 2805.59157894737 | 330.05045 | 0 | 0 | 4 |
| FPGA_SRAM_RDATA17 | 2060.67 | SIG_DML2_CON | 0 | 2805.59157894737 | 344.13189 | -14.08144 | 0 | 4 |
| FPGA_SRAM_RDATA16 | 2361.19 | SIG_DML2_CON | 0 | 2805.59157894737 | 394.31873 | -64.26828 | 0 | 4 |
| FPGA_SRAM_RDATA15 | 2555.24 | SIG_DML2_CON | 0 | 2805.59157894737 | 426.72508 | -96.67463 | -1 | 3 |
| FPGA_SRAM_RDATA14 | 2643.55 | SIG_DML2_CON | 0 | 2805.59157894737 | 441.47285 | -111.4224 | -1 | 3 |
| FPGA_SRAM_RDATA13 | 2783.77 | SIG_DML2_CON | 0 | 2805.59157894737 | 464.88959 | -134.83914 | -1 | 3 |
| FPGA_SRAM_RDATA12 | 3204.88 | SIG_DML2_CON | 0 | 2805.59157894737 | 535.21496 | -205.16451 | -2 | 2 |
| FPGA_SRAM_RDATA11 | 3450.88 | SIG_DML2_CON | 0 | 2805.59157894737 | 576.29696 | -246.24651 | -3 | 1 |
| FPGA_SRAM_RDATA10 | 3748.97 | SIG_DML2_CON | 0 | 2805.59157894737 | 626.07799 | -296.02754 | -3 | 1 |
| FPGA_SRAM_RDATA9 | 4128.87 | SIG_DML2_CON | 0 | 2805.59157894737 | 689.52129 | -359.47084 | -4 | 0 |
| FPGA_SRAM_RDATA8 | 2206.29 | SIG_DML2_CON | 0 | 2805.59157894737 | 368.45043 | -38.39998 | 0 | 4 |
| FPGA_SRAM_RDATA7 | 2387.63 | SIG_DML2_CON | 0 | 2805.59157894737 | 398.73421 | -68.68376 | 0 | 4 |
| FPGA_SRAM_RDATA6 | 2458.86 | SIG_DML2_CON | 0 | 2805.59157894737 | 410.62962 | -80.57917 | -1 | 3 |
| FPGA_SRAM_RDATA5 | 2562.97 | SIG_DML2_CON | 0 | 2805.59157894737 | 428.01599 | -97.96554 | -1 | 3 |
| FPGA_SRAM_RDATA4 | 2813.14 | SIG_DML2_CON | 0 | 2805.59157894737 | 469.79438 | -139.74393 | -1 | 3 |
| FPGA_SRAM_RDATA3 | 3162.41 | SIG_DML2_CON | 0 | 2805.59157894737 | 528.12247 | -198.07202 | -2 | 2 |
| FPGA_SRAM_RDATA2 | 3312.99 | SIG_DML2_CON | 0 | 2805.59157894737 | 553.26933 | -223.21888 | -2 | 2 |
| FPGA_SRAM_RDATA1 | 3670.76 | SIG_DML2_CON | 0 | 2805.59157894737 | 613.01692 | -282.96647 | -3 | 1 |
| FPGA_SRAM_RDATA0 | 3793.17 | SIG_DML2_CON | 0 | 2805.59157894737 | 633.45939 | -303.40894 | -3 | 1 |
| Matched Length Group #3 | ||||||||
| FPGA_SRAM_CQ_CLK_N | 1647 | SIG_DML3_CON | 1 | 2245.86894736842 | 275.049 | 0 | 0 | 4 |
| FPGA_SRAM_RDATA35 | 3261.71 | SIG_DML3_CON | 0 | 2245.86894736842 | 544.70557 | -269.65657 | -3 | 1 |
| FPGA_SRAM_RDATA34 | 3086.63 | SIG_DML3_CON | 0 | 2245.86894736842 | 515.46721 | -240.41821 | -3 | 1 |
| FPGA_SRAM_RDATA33 | 2746.72 | SIG_DML3_CON | 0 | 2245.86894736842 | 458.70224 | -183.65324 | -2 | 2 |
| FPGA_SRAM_RDATA32 | 2473.22 | SIG_DML3_CON | 0 | 2245.86894736842 | 413.02774 | -137.97874 | -1 | 3 |
| FPGA_SRAM_RDATA31 | 2417.51 | SIG_DML3_CON | 0 | 2245.86894736842 | 403.72417 | -128.67517 | -1 | 3 |
| FPGA_SRAM_RDATA30 | 1839.46 | SIG_DML3_CON | 0 | 2245.86894736842 | 307.18982 | -32.14082 | 0 | 4 |
| FPGA_SRAM_RDATA29 | 1790.92 | SIG_DML3_CON | 0 | 2245.86894736842 | 299.08364 | -24.03464 | 0 | 4 |
| FPGA_SRAM_RDATA28 | 1675.18 | SIG_DML3_CON | 0 | 2245.86894736842 | 279.75506 | -4.70605999999998 | 0 | 4 |
| FPGA_SRAM_RDATA27 | 1635.68 | SIG_DML3_CON | 0 | 2245.86894736842 | 273.15856 | 1.89044000000001 | 0 | 4 |
| FPGA_SRAM_RDATA26 | 3518.3 | SIG_DML3_CON | 0 | 2245.86894736842 | 587.5561 | -312.5071 | -4 | 0 |
| FPGA_SRAM_RDATA25 | 3180.23 | SIG_DML3_CON | 0 | 2245.86894736842 | 531.09841 | -256.04941 | -3 | 1 |
| FPGA_SRAM_RDATA24 | 2973.35 | SIG_DML3_CON | 0 | 2245.86894736842 | 496.54945 | -221.50045 | -2 | 2 |
| FPGA_SRAM_RDATA23 | 2635.3 | SIG_DML3_CON | 0 | 2245.86894736842 | 440.0951 | -165.0461 | -2 | 2 |
| FPGA_SRAM_RDATA22 | 2221.83 | SIG_DML3_CON | 0 | 2245.86894736842 | 371.04561 | -95.99661 | -1 | 3 |
| FPGA_SRAM_RDATA21 | 2003.05 | SIG_DML3_CON | 0 | 2245.86894736842 | 334.50935 | -59.4603499999999 | 0 | 4 |
| FPGA_SRAM_RDATA20 | 1848.85 | SIG_DML3_CON | 0 | 2245.86894736842 | 308.75795 | -33.70895 | 0 | 4 |
| FPGA_SRAM_RDATA19 | 1675.54 | SIG_DML3_CON | 0 | 2245.86894736842 | 279.81518 | -4.76617999999996 | 0 | 4 |
| FPGA_SRAM_RDATA18 | 1688.03 | SIG_DML3_CON | 0 | 2245.86894736842 | 281.90101 | -6.85200999999995 | 0 | 4 |
Jeremy W. Webb Graduate Student Electrical and Computer Engineering Department One Shields Avenue Davis, CA 95616
Last Modified: Monday, March 27, 2017 10:16:00 PM
