Today is: Tuesday October 15, 2024
Welcome to the MSEE Thesis Board DDR2 SDRAM Delay web page. This page
contains information on the approximate IODELAY taps required on the
DDR2 SDRAM Read and Write signals. The Perl code for used to implement
the table below is provided in a gzip'd tar-ball: ddr2_sdram_iodelay.tgz.
DDR2 SDRAM Signal IODELAY Taps:
- Matched Length Group #1: SIG_DML1_CON, Reference Signal: FPGA_DDR2_SDRAM_CK_P0
- Matched Length Group #2: SIG_DML2_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS0
- Matched Length Group #3: SIG_DML3_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS1
- Matched Length Group #1: SIG_DML4_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS2
- Matched Length Group #2: SIG_DML5_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS3
- Matched Length Group #3: SIG_DML6_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS4
- Matched Length Group #1: SIG_DML7_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS5
- Matched Length Group #2: SIG_DML8_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS6
- Matched Length Group #3: SIG_DML9_CON, Reference Signal: FPGA_DDR2_SDRAM_DQS7
| Signal Name | Length (Mils) | ML Group | Is Reference | Average Length (Mils) | Length (ps) | Added Delay (ps) | Number of Taps Needed | Number of Taps Needed (Normalized) |
|---|---|---|---|---|---|---|---|---|
| Matched Length Group #1 | ||||||||
| FPGA_DDR2_SDRAM_A0 | 2998.88 | SIG_DML1_CON | 0 | 3424.42433333333 | 500.81296 | 263.90175 | 3 | 3 |
| FPGA_DDR2_SDRAM_A1 | 2650.25 | SIG_DML1_CON | 0 | 3424.42433333333 | 442.59175 | 322.12296 | 4 | 4 |
| FPGA_DDR2_SDRAM_A2 | 2817.97 | SIG_DML1_CON | 0 | 3424.42433333333 | 470.60099 | 294.11372 | 3 | 3 |
| FPGA_DDR2_SDRAM_A3 | 2935.95 | SIG_DML1_CON | 0 | 3424.42433333333 | 490.30365 | 274.41106 | 3 | 3 |
| FPGA_DDR2_SDRAM_A4 | 2578.31 | SIG_DML1_CON | 0 | 3424.42433333333 | 430.57777 | 334.13694 | 4 | 4 |
| FPGA_DDR2_SDRAM_A5 | 3084.73 | SIG_DML1_CON | 0 | 3424.42433333333 | 515.14991 | 249.5648 | 3 | 3 |
| FPGA_DDR2_SDRAM_A6 | 2689.36 | SIG_DML1_CON | 0 | 3424.42433333333 | 449.12312 | 315.59159 | 4 | 4 |
| FPGA_DDR2_SDRAM_A7 | 2859.02 | SIG_DML1_CON | 0 | 3424.42433333333 | 477.45634 | 287.25837 | 3 | 3 |
| FPGA_DDR2_SDRAM_A8 | 3039.45 | SIG_DML1_CON | 0 | 3424.42433333333 | 507.58815 | 257.12656 | 3 | 3 |
| FPGA_DDR2_SDRAM_A9 | 3025.96 | SIG_DML1_CON | 0 | 3424.42433333333 | 505.33532 | 259.37939 | 3 | 3 |
| FPGA_DDR2_SDRAM_A10 | 3821.08 | SIG_DML1_CON | 0 | 3424.42433333333 | 638.12036 | 126.59435 | 1 | 1 |
| FPGA_DDR2_SDRAM_A11 | 2753.06 | SIG_DML1_CON | 0 | 3424.42433333333 | 459.76102 | 304.95369 | 3 | 3 |
| FPGA_DDR2_SDRAM_A12 | 3039.53 | SIG_DML1_CON | 0 | 3424.42433333333 | 507.60151 | 257.1132 | 3 | 3 |
| FPGA_DDR2_SDRAM_A13 | 4166.21 | SIG_DML1_CON | 0 | 3424.42433333333 | 695.75707 | 68.9576400000001 | 0 | 0 |
| FPGA_DDR2_SDRAM_BA0 | 4085.54 | SIG_DML1_CON | 0 | 3424.42433333333 | 682.28518 | 82.42953 | 1 | 1 |
| FPGA_DDR2_SDRAM_BA1 | 3795.98 | SIG_DML1_CON | 0 | 3424.42433333333 | 633.92866 | 130.78605 | 1 | 1 |
| FPGA_DDR2_SDRAM_BA2 | 3092.63 | SIG_DML1_CON | 0 | 3424.42433333333 | 516.46921 | 248.2455 | 3 | 3 |
| FPGA_DDR2_SDRAM_CASN | 4206.48 | SIG_DML1_CON | 0 | 3424.42433333333 | 702.48216 | 62.2325500000001 | 0 | 0 |
| FPGA_DDR2_SDRAM_CKE0 | 3972.22 | SIG_DML1_CON | 0 | 3424.42433333333 | 663.36074 | 101.35397 | 1 | 1 |
| FPGA_DDR2_SDRAM_CKE1 | 4002.67 | SIG_DML1_CON | 0 | 3424.42433333333 | 668.44589 | 96.26882 | 1 | 1 |
| FPGA_DDR2_SDRAM_ODT0 | 3864.74 | SIG_DML1_CON | 0 | 3424.42433333333 | 645.41158 | 119.30313 | 1 | 1 |
| FPGA_DDR2_SDRAM_ODT1 | 4270.34 | SIG_DML1_CON | 0 | 3424.42433333333 | 713.14678 | 51.56793 | 0 | 0 |
| FPGA_DDR2_SDRAM_RASN | 4007.72 | SIG_DML1_CON | 0 | 3424.42433333333 | 669.28924 | 95.4254700000001 | 1 | 1 |
| FPGA_DDR2_SDRAM_SN0 | 4098.98 | SIG_DML1_CON | 0 | 3424.42433333333 | 684.52966 | 80.1850500000002 | 1 | 1 |
| FPGA_DDR2_SDRAM_SN1 | 4272.83 | SIG_DML1_CON | 0 | 3424.42433333333 | 713.56261 | 51.1521 | 0 | 0 |
| FPGA_DDR2_SDRAM_WEN | 4242.59 | SIG_DML1_CON | 0 | 3424.42433333333 | 708.51253 | 56.20218 | 0 | 0 |
| FPGA_DDR2_SDRAM_CK_P0 | 4579.13 | SIG_DML1_CON | 1 | 3424.42433333333 | 764.71471 | 0 | 0 | 0 |
| FPGA_DDR2_SDRAM_CK_N0 | 4415 | SIG_DML1_CON | 0 | 3424.42433333333 | 737.305 | 27.40971 | 0 | 0 |
| FPGA_DDR2_SDRAM_CK_P1 | 4047.45 | SIG_DML1_CON | 0 | 3424.42433333333 | 675.92415 | 88.79056 | 1 | 1 |
| FPGA_DDR2_SDRAM_CK_N1 | 3897.8 | SIG_DML1_CON | 0 | 3424.42433333333 | 650.9326 | 113.78211 | 1 | 1 |
| Matched Length Group #2 | ||||||||
| FPGA_DDR2_SDRAM_DM0 | 4957.16 | SIG_DML2_CON | 0 | 4823.52181818182 | 827.84572 | 9.33028999999999 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQS0 | 5013.03 | SIG_DML2_CON | 1 | 4823.52181818182 | 837.17601 | 0 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQSN_NC0 | 5120.19 | SIG_DML2_CON | 0 | 4823.52181818182 | 855.07173 | -17.89572 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ0 | 5212.59 | SIG_DML2_CON | 0 | 4823.52181818182 | 870.50253 | -33.3265200000001 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ1 | 5287.59 | SIG_DML2_CON | 0 | 4823.52181818182 | 883.02753 | -45.8515200000001 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ2 | 5971.22 | SIG_DML2_CON | 0 | 4823.52181818182 | 997.19374 | -160.01773 | -2 | 0 |
| FPGA_DDR2_SDRAM_DQ3 | 5918.91 | SIG_DML2_CON | 0 | 4823.52181818182 | 988.45797 | -151.28196 | -1 | 1 |
| FPGA_DDR2_SDRAM_DQ4 | 4849.32 | SIG_DML2_CON | 0 | 4823.52181818182 | 809.83644 | 27.33957 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ5 | 4963.7 | SIG_DML2_CON | 0 | 4823.52181818182 | 828.9379 | 8.23811000000001 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ6 | 5252.29 | SIG_DML2_CON | 0 | 4823.52181818182 | 877.13243 | -39.95642 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ7 | 5525.77 | SIG_DML2_CON | 0 | 4823.52181818182 | 922.80359 | -85.6275800000001 | -1 | 1 |
| Matched Length Group #3 | ||||||||
| FPGA_DDR2_SDRAM_DM1 | 4747.95 | SIG_DML3_CON | 0 | 4629.45181818182 | 792.90765 | 56.75829 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQS1 | 5087.82 | SIG_DML3_CON | 1 | 4629.45181818182 | 849.66594 | 0 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQSN_NC1 | 5041.4 | SIG_DML3_CON | 0 | 4629.45181818182 | 841.9138 | 7.75213999999994 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ8 | 5025.85 | SIG_DML3_CON | 0 | 4629.45181818182 | 839.31695 | 10.3489899999998 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ9 | 5105.2 | SIG_DML3_CON | 0 | 4629.45181818182 | 852.5684 | -2.90246000000002 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ10 | 5191.29 | SIG_DML3_CON | 0 | 4629.45181818182 | 866.94543 | -17.27949 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ11 | 5591.27 | SIG_DML3_CON | 0 | 4629.45181818182 | 933.74209 | -84.0761500000001 | -1 | 0 |
| FPGA_DDR2_SDRAM_DQ12 | 4985.72 | SIG_DML3_CON | 0 | 4629.45181818182 | 832.61524 | 17.0506999999999 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ13 | 4870.79 | SIG_DML3_CON | 0 | 4629.45181818182 | 813.42193 | 36.2440099999999 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ14 | 5183.55 | SIG_DML3_CON | 0 | 4629.45181818182 | 865.65285 | -15.9869100000001 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ15 | 5180.95 | SIG_DML3_CON | 0 | 4629.45181818182 | 865.21865 | -15.55271 | 0 | 1 |
| Matched Length Group #4 | ||||||||
| FPGA_DDR2_SDRAM_DM2 | 3097.62 | SIG_DML4_CON | 0 | 3074.28545454546 | 517.30254 | 166.76954 | 2 | 3 |
| FPGA_DDR2_SDRAM_DQS2 | 4096.24 | SIG_DML4_CON | 0 | 3074.28545454546 | 684.07208 | 0 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQSN_NC2 | 4053.5 | SIG_DML4_CON | 0 | 3074.28545454546 | 676.9345 | 7.13757999999996 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ16 | 3213.96 | SIG_DML4_CON | 0 | 3074.28545454546 | 536.73132 | 147.34076 | 1 | 2 |
| FPGA_DDR2_SDRAM_DQ17 | 4673.29 | SIG_DML4_CON | 0 | 3074.28545454546 | 780.43943 | -96.36735 | -1 | 0 |
| FPGA_DDR2_SDRAM_DQ18 | 3385.15 | SIG_DML4_CON | 0 | 3074.28545454546 | 565.32005 | 118.75203 | 1 | 2 |
| FPGA_DDR2_SDRAM_DQ19 | 3360.45 | SIG_DML4_CON | 0 | 3074.28545454546 | 561.19515 | 122.87693 | 1 | 2 |
| FPGA_DDR2_SDRAM_DQ20 | 3098.27 | SIG_DML4_CON | 0 | 3074.28545454546 | 517.41109 | 166.66099 | 2 | 3 |
| FPGA_DDR2_SDRAM_DQ21 | 3005.61 | SIG_DML4_CON | 0 | 3074.28545454546 | 501.93687 | 182.13521 | 2 | 3 |
| FPGA_DDR2_SDRAM_DQ22 | 2996.25 | SIG_DML4_CON | 0 | 3074.28545454546 | 500.37375 | 183.69833 | 2 | 3 |
| FPGA_DDR2_SDRAM_DQ23 | 2933.04 | SIG_DML4_CON | 0 | 3074.28545454546 | 489.81768 | 194.2544 | 2 | 3 |
| Matched Length Group #5 | ||||||||
| FPGA_DDR2_SDRAM_DM3 | 3152.38 | SIG_DML5_CON | 0 | 2834.31545454545 | 526.44746 | -28.2463800000001 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQS3 | 2983.24 | SIG_DML5_CON | 1 | 2834.31545454545 | 498.20108 | 0 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQSN_NC3 | 3023.39 | SIG_DML5_CON | 0 | 2834.31545454545 | 504.90613 | -6.70505000000003 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ24 | 3390.75 | SIG_DML5_CON | 0 | 2834.31545454545 | 566.25525 | -68.0541700000001 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ25 | 3052.47 | SIG_DML5_CON | 0 | 2834.31545454545 | 509.76249 | -11.56141 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ26 | 3622.58 | SIG_DML5_CON | 0 | 2834.31545454545 | 604.97086 | -106.76978 | -1 | 0 |
| FPGA_DDR2_SDRAM_DQ27 | 3219.61 | SIG_DML5_CON | 0 | 2834.31545454545 | 537.67487 | -39.4737900000001 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ28 | 2853.83 | SIG_DML5_CON | 0 | 2834.31545454545 | 476.58961 | 21.61147 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ29 | 3098.43 | SIG_DML5_CON | 0 | 2834.31545454545 | 517.43781 | -19.23673 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ30 | 2847.6 | SIG_DML5_CON | 0 | 2834.31545454545 | 475.5492 | 22.65188 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ31 | 2916.43 | SIG_DML5_CON | 0 | 2834.31545454545 | 487.04381 | 11.15727 | 0 | 1 |
| Matched Length Group #6 | ||||||||
| FPGA_DDR2_SDRAM_DM4 | 3182.03 | SIG_DML6_CON | 0 | 3086.19090909091 | 531.39901 | 6.71172999999987 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQS4 | 3222.22 | SIG_DML6_CON | 1 | 3086.19090909091 | 538.11074 | 0 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQSN_NC4 | 3270.92 | SIG_DML6_CON | 0 | 3086.19090909091 | 546.24364 | -8.13290000000006 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ32 | 3229.13 | SIG_DML6_CON | 0 | 3086.19090909091 | 539.26471 | -1.15397000000007 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ33 | 3155.01 | SIG_DML6_CON | 0 | 3086.19090909091 | 526.88667 | 11.2240699999999 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ34 | 3607.15 | SIG_DML6_CON | 0 | 3086.19090909091 | 602.39405 | -64.28331 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ35 | 4247.09 | SIG_DML6_CON | 0 | 3086.19090909091 | 709.26403 | -171.15329 | -2 | 0 |
| FPGA_DDR2_SDRAM_DQ36 | 2940.51 | SIG_DML6_CON | 0 | 3086.19090909091 | 491.06517 | 47.0455699999999 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ37 | 2957.14 | SIG_DML6_CON | 0 | 3086.19090909091 | 493.84238 | 44.26836 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ38 | 3501.94 | SIG_DML6_CON | 0 | 3086.19090909091 | 584.82398 | -46.71324 | 0 | 2 |
| FPGA_DDR2_SDRAM_DQ39 | 3857.18 | SIG_DML6_CON | 0 | 3086.19090909091 | 644.14906 | -106.03832 | -1 | 1 |
| Matched Length Group #7 | ||||||||
| FPGA_DDR2_SDRAM_DM5 | 3549.72 | SIG_DML7_CON | 0 | 3250.59363636364 | 592.80324 | -4.55909999999994 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQS5 | 3522.42 | SIG_DML7_CON | 1 | 3250.59363636364 | 588.24414 | 0 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQSN_NC5 | 3405.06 | SIG_DML7_CON | 0 | 3250.59363636364 | 568.64502 | 19.59912 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ40 | 3996.72 | SIG_DML7_CON | 0 | 3250.59363636364 | 667.45224 | -79.2080999999999 | -1 | 0 |
| FPGA_DDR2_SDRAM_DQ41 | 3555.78 | SIG_DML7_CON | 0 | 3250.59363636364 | 593.81526 | -5.57112000000006 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ42 | 3842.33 | SIG_DML7_CON | 0 | 3250.59363636364 | 641.66911 | -53.42497 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ43 | 4029.84 | SIG_DML7_CON | 0 | 3250.59363636364 | 672.98328 | -84.73914 | -1 | 0 |
| FPGA_DDR2_SDRAM_DQ44 | 3311.4 | SIG_DML7_CON | 0 | 3250.59363636364 | 553.0038 | 35.2403399999999 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ45 | 3135.08 | SIG_DML7_CON | 0 | 3250.59363636364 | 523.55836 | 64.68578 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ46 | 3605.04 | SIG_DML7_CON | 0 | 3250.59363636364 | 602.04168 | -13.79754 | 0 | 1 |
| FPGA_DDR2_SDRAM_DQ47 | 3325.56 | SIG_DML7_CON | 0 | 3250.59363636364 | 555.36852 | 32.87562 | 0 | 1 |
| Matched Length Group #8 | ||||||||
| FPGA_DDR2_SDRAM_DM6 | 2854.88 | SIG_DML8_CON | 0 | 2825.76 | 476.76496 | 69.47534 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQS6 | 3270.9 | SIG_DML8_CON | 1 | 2825.76 | 546.2403 | 0 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQSN_NC6 | 3124.1 | SIG_DML8_CON | 0 | 2825.76 | 521.7247 | 24.5156000000001 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ48 | 3316.24 | SIG_DML8_CON | 0 | 2825.76 | 553.81208 | -7.57177999999999 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ49 | 3187.81 | SIG_DML8_CON | 0 | 2825.76 | 532.36427 | 13.87603 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ50 | 3301.99 | SIG_DML8_CON | 0 | 2825.76 | 551.43233 | -5.19202999999993 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ51 | 3414.35 | SIG_DML8_CON | 0 | 2825.76 | 570.19645 | -23.95615 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ52 | 2930.49 | SIG_DML8_CON | 0 | 2825.76 | 489.39183 | 56.8484700000001 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ53 | 3105.69 | SIG_DML8_CON | 0 | 2825.76 | 518.65023 | 27.59007 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ54 | 2867.57 | SIG_DML8_CON | 0 | 2825.76 | 478.88419 | 67.35611 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ55 | 2980.24 | SIG_DML8_CON | 0 | 2825.76 | 497.70008 | 48.54022 | 0 | 0 |
| Matched Length Group #9 | ||||||||
| FPGA_DDR2_SDRAM_DM7 | 4052.38 | SIG_DML9_CON | 0 | 3542.48818181818 | 676.74746 | -39.68421 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQS7 | 3814.75 | SIG_DML9_CON | 1 | 3542.48818181818 | 637.06325 | 0 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQSN_NC7 | 3706.51 | SIG_DML9_CON | 0 | 3542.48818181818 | 618.98717 | 18.0760799999999 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ56 | 3984.63 | SIG_DML9_CON | 0 | 3542.48818181818 | 665.43321 | -28.36996 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ57 | 4208.12 | SIG_DML9_CON | 0 | 3542.48818181818 | 702.75604 | -65.6927899999999 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ58 | 4026.51 | SIG_DML9_CON | 0 | 3542.48818181818 | 672.42717 | -35.36392 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ59 | 3832.92 | SIG_DML9_CON | 0 | 3542.48818181818 | 640.09764 | -3.03439000000003 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ60 | 3930.77 | SIG_DML9_CON | 0 | 3542.48818181818 | 656.43859 | -19.3753400000001 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ61 | 3748.47 | SIG_DML9_CON | 0 | 3542.48818181818 | 625.99449 | 11.06876 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ62 | 3768.33 | SIG_DML9_CON | 0 | 3542.48818181818 | 629.31111 | 7.75214000000005 | 0 | 0 |
| FPGA_DDR2_SDRAM_DQ63 | 3708.73 | SIG_DML9_CON | 0 | 3542.48818181818 | 619.35791 | 17.70534 | 0 | 0 |
Jeremy W. Webb Graduate Student Electrical and Computer Engineering Department One Shields Avenue Davis, CA 95616
Last Modified: Monday, March 27, 2017 10:16:16 PM
