i DDR2 SDRAM Signal Delay Values

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Welcome to the MSEE Thesis Board DDR2 SDRAM Delay web page. This page contains information on the approximate IODELAY taps required on the DDR2 SDRAM Read and Write signals. The Perl code for used to implement the table below is provided in a gzip'd tar-ball: ddr2_sdram_iodelay.tgz.

Jeremy W. Webb
Graduate Student
Electrical and Computer Engineering Department
One Shields Avenue
Davis, CA 95616

Last Modified: Monday, March 27, 2017 10:16:16 PM