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Welcome to the MSEE Thesis Board ADC Delay web page. This page
contains information on the approximate IODELAY taps required on the
ADC Read and Write signals. The Perl code for used to implement
the table below is provided in a gzip'd tar-ball: adc_iodelay.tgz.
ADC Signal IODELAY Taps:
- Matched Length Group #1: SIG_DML1_CON, Reference Signal: FPGA_ADC_DATA_RDY_P
| Signal Name | Length (Mils) | ML Group | Is Reference | Average Length (Mils) | Length (ps) | Added Delay (ps) | Number of Taps Needed | Number of Taps Needed (Normalized) |
|---|---|---|---|---|---|---|---|---|
| Matched Length Group #1 | ||||||||
| FPGA_ADC_OVR_P | 4838.18 | ADC_DIFF | 0 | 4777.59833333333 | 807.97606 | 41.06029 | 0 | 1 |
| FPGA_ADC_OVR_N | 4781.46 | ADC_DIFF | 0 | 4777.59833333333 | 798.50382 | 50.5325300000001 | 0 | 1 |
| FPGA_ADC_DATA_RDY_P | 5084.05 | ADC_DIFF | 1 | 4777.59833333333 | 849.03635 | 0 | 0 | 1 |
| FPGA_ADC_DATA_RDY_N | 5084.41 | ADC_DIFF | 0 | 4777.59833333333 | 849.09647 | -0.0601199999999835 | 0 | 1 |
| FPGA_ADC_DATA_P15 | 4181.28 | ADC_DIFF | 0 | 4777.59833333333 | 698.27376 | 150.76259 | 1 | 2 |
| FPGA_ADC_DATA_N15 | 4161.74 | ADC_DIFF | 0 | 4777.59833333333 | 695.01058 | 154.02577 | 1 | 2 |
| FPGA_ADC_DATA_P14 | 4911.44 | ADC_DIFF | 0 | 4777.59833333333 | 820.21048 | 28.8258700000001 | 0 | 1 |
| FPGA_ADC_DATA_N14 | 4933.09 | ADC_DIFF | 0 | 4777.59833333333 | 823.82603 | 25.21032 | 0 | 1 |
| FPGA_ADC_DATA_P13 | 4431.04 | ADC_DIFF | 0 | 4777.59833333333 | 739.98368 | 109.05267 | 1 | 2 |
| FPGA_ADC_DATA_N13 | 4418.19 | ADC_DIFF | 0 | 4777.59833333333 | 737.83773 | 111.19862 | 1 | 2 |
| FPGA_ADC_DATA_P12 | 5105.24 | ADC_DIFF | 0 | 4777.59833333333 | 852.57508 | -3.53872999999987 | 0 | 1 |
| FPGA_ADC_DATA_N12 | 5028.53 | ADC_DIFF | 0 | 4777.59833333333 | 839.76451 | 9.27184000000011 | 0 | 1 |
| FPGA_ADC_DATA_P11 | 4849.78 | ADC_DIFF | 0 | 4777.59833333333 | 809.91326 | 39.12309 | 0 | 1 |
| FPGA_ADC_DATA_N11 | 4929.46 | ADC_DIFF | 0 | 4777.59833333333 | 823.21982 | 25.8165300000001 | 0 | 1 |
| FPGA_ADC_DATA_P10 | 5500.59 | ADC_DIFF | 0 | 4777.59833333333 | 918.59853 | -69.56218 | 0 | 1 |
| FPGA_ADC_DATA_N10 | 5581 | ADC_DIFF | 0 | 4777.59833333333 | 932.027 | -82.99065 | -1 | 0 |
| FPGA_ADC_DATA_P9 | 4717.87 | ADC_DIFF | 0 | 4777.59833333333 | 787.88429 | 61.15206 | 0 | 1 |
| FPGA_ADC_DATA_N9 | 4737.86 | ADC_DIFF | 0 | 4777.59833333333 | 791.22262 | 57.8137300000001 | 0 | 1 |
| FPGA_ADC_DATA_P8 | 5423 | ADC_DIFF | 0 | 4777.59833333333 | 905.641 | -56.60465 | 0 | 1 |
| FPGA_ADC_DATA_N8 | 5384.44 | ADC_DIFF | 0 | 4777.59833333333 | 899.20148 | -50.1651299999999 | 0 | 1 |
| FPGA_ADC_DATA_P7 | 4994.17 | ADC_DIFF | 0 | 4777.59833333333 | 834.02639 | 15.00996 | 0 | 1 |
| FPGA_ADC_DATA_N7 | 5013.08 | ADC_DIFF | 0 | 4777.59833333333 | 837.18436 | 11.85199 | 0 | 1 |
| FPGA_ADC_DATA_P6 | 4770.75 | ADC_DIFF | 0 | 4777.59833333333 | 796.71525 | 52.3211 | 0 | 1 |
| FPGA_ADC_DATA_N6 | 4731.44 | ADC_DIFF | 0 | 4777.59833333333 | 790.15048 | 58.8858700000001 | 0 | 1 |
| FPGA_ADC_DATA_P5 | 4352.98 | ADC_DIFF | 0 | 4777.59833333333 | 726.94766 | 122.08869 | 1 | 2 |
| FPGA_ADC_DATA_N5 | 4330.28 | ADC_DIFF | 0 | 4777.59833333333 | 723.15676 | 125.87959 | 1 | 2 |
| FPGA_ADC_DATA_P4 | 4684.41 | ADC_DIFF | 0 | 4777.59833333333 | 782.29647 | 66.7398800000001 | 0 | 1 |
| FPGA_ADC_DATA_N4 | 4700.57 | ADC_DIFF | 0 | 4777.59833333333 | 784.99519 | 64.0411600000001 | 0 | 1 |
| FPGA_ADC_DATA_P3 | 4282.2 | ADC_DIFF | 0 | 4777.59833333333 | 715.1274 | 133.90895 | 1 | 2 |
| FPGA_ADC_DATA_N3 | 4306.9 | ADC_DIFF | 0 | 4777.59833333333 | 719.2523 | 129.78405 | 1 | 2 |
| FPGA_ADC_DATA_P2 | 4825.42 | ADC_DIFF | 0 | 4777.59833333333 | 805.84514 | 43.1912100000001 | 0 | 1 |
| FPGA_ADC_DATA_N2 | 4894.9 | ADC_DIFF | 0 | 4777.59833333333 | 817.4483 | 31.5880500000001 | 0 | 1 |
| FPGA_ADC_DATA_P1 | 4284.51 | ADC_DIFF | 0 | 4777.59833333333 | 715.51317 | 133.52318 | 1 | 2 |
| FPGA_ADC_DATA_N1 | 4301.71 | ADC_DIFF | 0 | 4777.59833333333 | 718.38557 | 130.65078 | 1 | 2 |
| FPGA_ADC_DATA_P0 | 4725.53 | ADC_DIFF | 0 | 4777.59833333333 | 789.16351 | 59.8728400000001 | 0 | 1 |
| FPGA_ADC_DATA_N0 | 4712.04 | ADC_DIFF | 0 | 4777.59833333333 | 786.91068 | 62.12567 | 0 | 1 |
Jeremy W. Webb Graduate Student Electrical and Computer Engineering Department One Shields Avenue Davis, CA 95616
Last Modified: Monday, March 27, 2017 10:17:42 PM
